To save precious layout space or increase interconnection efficiency, multiple chips of integrated circuits (ICs) can be stacked together as a single IC package. To that end, a three-dimensional (3D) stack packaging technology is used to package the chips of integrated circuits. Through-silicon vias (TSVs) are widely used to accomplish the 3D stack packaging technology. A through-silicon via is a vertical conductive via completely passing through a silicon wafer, a silicon board, a substrate of any material or die. Nowadays, a 3D integrated circuit (3D IC) is applied to a lot of fields such as memory stacks, image sensors or the like.
Compared to a single transistor or a single interconnect metal line, a through-silicon via comes with a size of hundred fold or more. To share the same manufacturing process with integrated circuits would mean difficulties to control process uniformity and/or keep process window. Furthermore, the gigantic TSVs would produce mechanical stress and electrical interference affecting the devices around them. Hence, there is a need to completely eliminate or at least reduce this issue.